This invention relates to integrated-circuit chips and, more particularly, to an assembly that includes multiple such chips interconnected by means of a conductive pattern formed on a wafer.
It is known to utilize a pattern of lithographically formed conductors on a semiconductor wafer to interconnect a number of semiconductor chips and to connect the chips to input/output pads on the wafer. In some cases, the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface. In other cases, the chips are fabricated in the wafer as integral parts thereof. Herein, all of these and similar arrangements, including arrangements that include more than one wafer, will be referred to as wafer-scale-integrated (WSI) assemblies.
WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard printed-circuit board. In such a standard assembly, the size of the chip package limits the density of circuits in a system. By contrast, in a WSI assembly, circuits can be packaged extremely closely on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths.
WSI assemblies can also improve system reliability. This is so because the major failure sites in conventional electronic assemblies are the connections between different packaging levels: for example, between chips and packages, between packages and boards, and between boards and cables. In a WSI assembly, the placement and interconnection of multiple chips on a single wafer in an integrated array greatly reduces the number and type of these interlevel connections.
In a WSI assembly, conductive interconnects on the order of a few micrometers thick and ten or so micrometers wide formed on dielectric layers roughly five to twenty micrometers thick have the potential for serving as high-speed transmission lines. But signal lines of such small cross section have relatively high resistance. In practice, interconnects in a typical WSI assembly exhibit a total line resistance comparable to the characteristic impedance of the line. Such a line is commonly referred to as "lossy".
It is generally not feasible to terminate a lossy WSI interconnect line with a properly sized terminating resistor. This is so because of signal attenuation and power consumption considerations. (A properly selected terminating resistor would of course allow the line to operate at very high pulse repetition rates without the reflectances and resonances that typically lead to signal instabilities and degradation.)
Accordingly, for a nonresistively terminated lossy line in a WSI assembly, operation is usually limited to frequencies considerably less than the resonance limit of the line, that is, the frequency at which the length of the line equals a quarter wavelength. In an assembly that includes some relatively long lines (e.g., about 18 centimeters long) the goal of avoiding signal instabilities and degradation on any of the lines thus leads to imposing an undesirably low frequency limit on the overall speed of operation of the assembly.
Accordingly, considerable technical efforts have been directed at trying to improve the performance of WSI assemblies by optimizing the structure of the interconnect lines thereof. It was recognized that these efforts, if successful, had the potential for providing highly reliable low-cost WSI systems characterized by extremely high speed.